1. Field of Invention
This invention relates generally to electronics, and more particularly to a programmable floating gate circuit for generating a voltage reference.
2. Description of Related Art
Programmable analog floating gate circuits have been used since the early 1980's in applications that only require moderate absolute voltage accuracy over time, e.g., an absolute voltage accuracy of 100–200 mV over time. Such devices are conventionally used to provide long-term non-volatile storage of charge on a floating gate. A floating gate is an island of conductive material that is electrically isolated from a substrate but capacitively coupled to the substrate. Typically, a floating gate forms the gate of an MOS (metal-oxide semiconductor) transistor that is used to read the level of charge on the floating gate without causing any leakage of charge therefrom.
Various means are known in the art for introducing charge onto a floating gate and for removing the charge from the floating gate. Once the floating gate has been programmed at a particular charge level, it remains at that level essentially permanently, because the floating gate is surrounded by an insulating material which acts as a barrier to discharging of the floating gate. Charge is typically coupled to the floating gate using hot electron injection or electron tunneling. Charge is typically removed from the floating gate by exposure to radiation (UV light, x-rays), avalanched injection, or Fowler-Nordheim electron tunneling. The use of electrons emitted from a cold conductor was first described in an article entitled Electron Emission in Intense Electric Fields by R. H. Fowler and Dr. L. Nordheim, Royal Soc. Proc., A, Vol. 119 (1928). Use of this phenomenon in electron tunneling through an oxide layer is described in an article entitled Fowler-Nordheim Tunneling into Thermally Grown SiO2 by M. Lenzlinger and E. H. Snow, Journal of Applied Physics, Vol. 40, No. 1 (January, 1969), both of which are incorporated herein by reference. Such analog floating gate circuits have been used, for instance, in digital nonvolatile memory devices and in analog nonvolatile circuits including voltage reference, Vcc sense, and power-on reset circuits.
The output voltage, Vo, of a floating gate analog voltage (FGA) reference can typically be set to any level between 0 and about 8V DC. For example, a FGA reference can be set accurately to Vo=100 mV if desired. However, in order for the reference to work properly on a very low supply voltage Vcc, such as 1V, the internal MOS gate voltages need to be less than ˜1V, such that the MOS transistors are enabled to operate in the high gain, low current prethreshold region. Devices that can be constructed using a thick oxide floating gate EEPROM (electrical-erasable programmable read-only memory) process limit how large a negative voltage can be generated on a chip, which makes it difficult to set the voltage on a floating gate negative or close to 0V directly during a set operation using the dual conduction electron tunneling FGA reference set operation, as described in patent application Ser. No. 10/338,189. Consequently, shifting the voltage level of a floating gate down after a set operation can be used to enable the floating gate to be accurately set to a more positive voltage during a set operation, and then shifted down to a lower voltage for read operations with a low supply voltage Vcc.
Floating gate level shifting is a well-known technique for programming and erasing EEPROM memory cells. A direct write EEPROM memory cell uses a coupling capacitor between the bit line and the floating gate as well as the poly2-poly1 capacitance between the word line and the floating gate to couple the floating gate negative after programming the cell. See, for example, U.S. Pat. No. 4,752,912. When a direct write EEPROM cell is programmed, the bit line is taken to about 14V, the word line is taken to +20V, the poly1 deselect line is taken to −3V, and the floating gate is set to approximately +8.5V. After programming, the floating gate is capacitively coupled down by about 70% of the 14V on the bit line (−9.8V) and by about 10% of the 20V on the word line (−2V) and coupled up by about 10% of the 7V difference on the deselect line (+0.7), such that the floating gate ends up with a voltage level of about −3.5V. This turns off the floating gate transistor by several volts to assure that no current flows in programmed EEPROM cells during a read operation. Several volts of negative programmed floating gate margin help assure that all of the programmed cells are off even with cell to cell variations and after many write cycles.
Various floating gate level shift circuits have been proposed to allow digital and analog circuits to operate at low Vcc by shifting the equivalent input transistor threshold lower during operation. In one solution, the floating gate level shift circuit has a floating gate with 2 coupling capacitor inputs. The charge level on the floating gate is initially set to 0 using UV exposure. Then, a positive Vbias is applied to the second capacitor input to the floating gate. The positive Vbias raises the voltage on the floating gate transistor close to Vt (threshold voltage), which reduces the DC voltage needed on the first coupling capacitor to turn on the transistor. This effectively “reduces the Vt” of the floating gate transistor as seen by the first coupling capacitor, which allows the circuit to work with lower input and supply voltages.
In another solution, floating gate MOS devices called FGUVMOS devices (floating gate ultraviolet metal oxide semiconductor), the floating gates are set by exposing the circuit to UV light, with ˜Vcc/2 applied to all the signal inputs. Once set in this manner, FGUVMOS devices have low “effective Vt” and can be operated at very low supply voltages. However, FGUVMOS devices require a very long (many minutes) UV exposure time to set each product, which is not practical for manufacturing accurate voltage references and comparators that operate on low Vcc.
Accordingly, it is desirable to provide a floating gate level shift circuit and method that generates a highly accurate voltage reference which can operate on a low supply voltage.